Circuit boards, especially computer system boards, are complex structures wherein nodes on either side of the board are conductively linked into a multiplicity of "nets." The word "net" is used herein to refer to a set of nodes on the board that are in conductive communication. Boards typically are comprised of a sandwich of layers, some conductive, some insulating. The nets may extend through, or on, either surface or any layer. Complex systems, such as personal computers, utilize multi-layer boards, including various power and ground planes and numerous interconnect layers, all of which are separated by insulating layers.
Upon occasion it becomes useful to determine, independently from any design specifications or other information, the actual nets on a board or a portion of a board. Such information might be useful, for instance, for the purpose of verifying that actual nets agree with the design specifications or for reverse engineering. While a simple visual inspection is easiest, the traces, or means of conductive communication on the interconnect layers between the nodes, are largely indecipherable visually when a multi-layer board is utilized. The interconnect layers are not visible through the insulating layers and so simple visual tracing is impossible.
The existing method used to determine nets among nodes of interest on a circuit board is implemented by applying a source of voltage to one node and connecting sequentially every other node of interest with a current sensing probe to determine whether the circuit closes. If the circuit closes, the two nodes are part of the same net. This is commonly referred to as a continuity test or buzzing out a board.
The problem with the above technique is that, for one sequential pass over the board, no information is gained as to the proper net of the nodes where no current is detected. One sequential pass results in the determination of only one net. Determining a second net thus requires a second pass over the remaining nodes of interest, applying the voltage source to one of the remaining nodes. This procedure must be performed in an iterative loop until all of the nodes have been examined. Given the complexity of modern circuit boards, this can be a very lengthy process. It is therefore clearly desirable to have a technique to speed up the process.